| 摘要 |
PURPOSE:To execute data transfer without providing waiting time to an I/O control device by using a flip flop circuit to be set up at the time of a DMA transfer request from a microprocessor and reset at the completion of data transfer. CONSTITUTION:When a DMA request is generated in a program, the microprocessor sets up a flip flop (FF) 52. After setting up the FF52, the 2nd bus occupation request signal is sent to the microprocessor 1. After ending an instruction in executing, the microprocessor 1 sends a bus occupation approval signal. If the FF52 is still set up as it is, a DMA control part receives the bus occupation approval simultaneously with the sending of the 1st bus occupation request signal and an I/O control device 6 also receives the DMA approval signal. A DAM completion signal resets simultaneously the FF52. |
