| 摘要 |
PURPOSE:To reduce considerably the number of hardwares by controlling main memory access from plural arithmetic processors and plural I/O proccessors and communication among respective processors only by one system control unit. CONSTITUTION:Memory access requests from respective units 2-5 are set up in request receiving circuits 20-23 in an SCU1. The request receiving circuits 20- 23 check whether the addresses of the received memory access requests are included in a specified area or not. If a certain address exceeds the access range, the outarea access error is reported to the requested unit through an answering circuit 24. If the access requests are included in the specified area, a control circuit decides the priority of respective requests in accordance with the signals from the request receiving circuits 20-23, selects the request having the highest priority and sends the selected request to an MMU6 through a request sending circuit 25. |
