发明名称 RECEIVING SIGNAL OFF DETECTING CIRCUIT
摘要 <p>PURPOSE:To detect 'OFF' of the receiving signal by comparing the output of a peak detecting device with the constant reference value, in the receiving circuit using a PLL circuit. CONSTITUTION:When a receiving signal is off, a noise is inputted to an input terminal 1, and therefore, a phase comparator 2 outputs the signal in accordance with the phase difference between the noise and the output of a voltage control oscillating device 4. The peak value is detected by a peak value detecting device 5, a comparator 6 compares the output of a detecting device 5 with a constant reference value, and when the output exceeds the reference value, the signal to show the receiving signal 'off' is outputted from the output terminal 7. Thus, when an automatic gain adjusting circuit is used, the receiving signal 'off' can be detected.</p>
申请公布号 JPS61161054(A) 申请公布日期 1986.07.21
申请号 JP19850001959 申请日期 1985.01.09
申请人 NEC CORP 发明人 KURIYAMA NOBUMI
分类号 H04L25/02;H04L1/20;H04L7/00 主分类号 H04L25/02
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