| 摘要 |
PURPOSE:To enhance reliability and yield of a semiconductor integrated circuit device by a method wherein an MISFET for checking of latch locking having short channel length and high transconductance is provided to the part being apt to generate the rise of electric potential of a semiconductor substrate. CONSTITUTION:An MISFET for checking of latch locking (a p-channel MISFET) QA is constructed of a gate electrode 5, an insulating film 4, a semiconductor substrate 1 and a semiconductor region 7C to be used as a source region or a drain region, and a semiconductor region 6C to be formed with the channel region thereof. Because channel length Lg thereof can be controlled according to the diffusion speed of impurities for formation of the semiconductor regions 6C, 7C, channel length can be formed extremely short, and high transconductance (gm) can be obtained. When an external noise voltage to exceed earth potential VSS is generated, the MISFET for checking of latch locking QA is made to be in the ''ON'' condition to remove the external noise voltage of the earth potential VSS or more. Accordingly, a latch locking phenomenon can be checked. |
