发明名称 FORMATION FOR MULTILAYER WIRING STRUCTURE
摘要 PURPOSE:To flatly form a second-layer wiring layer and to prevent from disconnecting by a method wherein a first-layer wiring layer of a large thickness is formed on the surface of a device and after an interlayer insulating layer was formed thereon, the first-layer wiring layer is made to expose by removing the interlayer insulating layer formed thereon and the exposed part of the first-layer wiring layer is removed by performing an etching. CONSTITUTION:A first-layer wiring layer 3 is formed on a silicon substrate 1 through an insulating film 2. At this time, the first-layer wiring layer 3 is formed thicker than the final thickness thereof at a time when an element in this multilayer wiring structure is completed. After this, an interlayer insulating layer 4 is formed on the whole surface. The surface of the interlayer insulating layer 4 is coated with a photo resist film 5. After this, the resist film 5 and the interlayer insulating layer 4 are removed in order by performing an etching and the thickness of the interlayer insulating layer 4 is removed to the thickness of the first-layer wiring layer 3 at a time when the element is completed. The first-layer wiring layer 3 made to expose in the way during the above-mentioned process is performed an etching up to become the final thickness thereof at a time when the element is completed with carbon tetrachloride, etc. After this, an insulant of the same kind as the interlayer insulating layer 4 is deposited on the interlayer insulating layer 4, and lastly, a second-layer wiring layer 6 is formed.
申请公布号 JPS60152043(A) 申请公布日期 1985.08.10
申请号 JP19840008146 申请日期 1984.01.20
申请人 SUMITOMO DENKI KOGYO KK 发明人 HORI MINORU;IDA JIROU
分类号 H01L21/3205;(IPC1-7):H01L21/88 主分类号 H01L21/3205
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