发明名称 MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To reduce burden of software and make synchronization accurately by starting a program cycle by a clock signal from a clock device commanded by one of plural processors. CONSTITUTION:Start stop control and setting control of period of generation of clock signals CL of a clock device 9 are made by a master CPU1. Period of the clock signals CL is set to a period longer to some degree than any of program cycles of the master CPU1 and slave CPU2-3. The clock signals CL are inputted to each CPU as interruption signals. Each CPU starts its own program processing simultaneously with inputting of the clock signal CL, and when its own program cycle is finished, makes idling operation, and when next clock signal CL is inputted, starts processing of own next program again.
申请公布号 JPS60151775(A) 申请公布日期 1985.08.09
申请号 JP19840007995 申请日期 1984.01.19
申请人 CHIYUUSHIYOU KIGIYOU SHINKOU JIGIYOUDAN 发明人 YAMAMOTO YUTAKA
分类号 G05B15/02;G05B19/18;G05B19/414;G06F9/52;G06F15/16;G06F15/17;G06F15/177 主分类号 G05B15/02
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