| 摘要 |
<p>The circuit has a plurality of input terminals (T0-T3) jointly connected to a common output terminal (TS). Each input terminal has a transfer MOS transistor (Q4, Q5, Q6, Q7) isolating this input terminal from other terminals at non-active state, and is connected to the common output terminal when an input signal is applied to the input terminal. A buffer circuit (I0, I1, I2, I3) is inserted between the input terminal and the gate of the MOS transistor, is driven by the input signal itself and provides a driving signal to the gate electrode of the MOS transistor, to make the MOS transistor conductive so as to transmit the inputed signal with almost perfectly preserved signal profile and extremely small time lag. This transmission circuit is applicable to transmit word line signals (o0, o1, o2, o3) to rows of storage cells in a storage device, in particular to transmit a word line signal simultaneously to a selected row of a real cell, to rows of reference cells and to a row of dummy cells in a multi-state ROM. </p> |
