| 摘要 |
<p>After detecting a leading edge of a stop control signal (STBY) supplied from an external circuit, an oscillation output signal (OSC) is cut off at an input side of a frequency divider (24) in synchronism with the first leading edge of a clock signal (CLK) generated from the frequency divider (24), thereby stopping the generation of clock signals (CLK). The stopping of the clock signal generating operation is released in such a manner that, immediately after a trailing edge of an external control signal (STBY) is detected, an internal state of the frequency divider (24) is initialized, and the oscillation output signal (OSC) which has been cut off is supplied to the frequency divider (24) again, thereby generating a proper clock signal (CLK).</p> |
