| 摘要 |
PURPOSE:To use a device with a slow operating speed by providing a single oscillating source, a prime number frequency division circuit and a digital multiple circuit connected in cascade to the prime number frequency division circuit. CONSTITUTION:An output of a crystal oscillator 1' outputting a frequency of 1/2 of an original frequency F0 is amplified by a buffer 10, inverted by an inverter buffer 11, an output of the buffer 10 is frequency-divided by 1/3 at a 1/3 frequency division counter 3, frequency-divided by 1/5 at a 1/5 frequency division counter 4, the 1/3 frequency-division and 1/5 frequency division output is multiplied digitally by multiplication circuits 12, 13 comprising D flip-flops 14, 17, shift registers 15, 18 and an AND/OR circuits 16, 17. Thus, a 1/2 frequency division output 31, a 1/3 frequency division output 32 and a 1/5 frequency division output 33 to the original oscillating frequency F0 are obtained.
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