| 摘要 |
PURPOSE:To realize a low source resistance and to provide a high withstand voltage for drain by a method wherein a very short distance between regions for gate and source and a distance between regions for gate and drain that is necessary for the attainment of a desired voltage-withstanding capability are determined by self-alignment in the first photoetching process. CONSTITUTION:Si<+> ions are driven into the surface of a semi-insulating GaAs substrate 1 for the selective formation of an ion-injected layer 2 to serve as an N type activation layer, which is then coated with an SiO2 film 11. In a process to follow, a photoresist film 12 is provided, wherein openings, 13S, 13D, 13G are created in locations planned for a source, drain, gate. The SiO2 film 11 is selectively removed by etching from regions for the source and drain. Si<+> ions are implanted for the formation of regions 14s, 14d implanted with high-density Si. The SiO2 film 11 is removed from the inside of the gate opening 13G by etching, and the photoresist film 12 is removed. By annealing, an N<+> source region 14S', N<+> drain region 14D', N type activation layer 2' are formed. Finally, a gate electrode 15G, source electrode 15S, drain electrode 15D are built. |
