| 摘要 |
PURPOSE:To generate a stable clock by controlling the internal state of a frequency divider even if rapid phase change such as a skew error takes place in a synchronizing signal to absorb the phase fluctuation. CONSTITUTION:The time interval between the initial internal state D and the 2nd internal state D is a time width generated as a skew error from the point of time of generation of a skew until a control signal 32 is given to a 1/N frequency divider 5 from the observation of the internal state 28, then the clock over-count is compensated. Thus, even if a skew is generated, the relation of phase between an output phase of the 1/N frequency divider 5 and the phase of an external synchronizing signal 1 is coincident with the two phase relations when a PLL is operated stably. Then only the phase shift due to skew error is compensated, the phase of a trapezoidal wave 27 and the phase of the synchronizing signal 1 afterward are at a stable position, and even if the sampling is conducted at a PC2 after correction of the internal state of the 1/N frequency divider 5, no effect is given onto the oscillating frequency of a VCO4 with an error voltage of steadly-state. Thus, no unstable regions of the PLL is caused. |
