| 摘要 |
PURPOSE:To decrease the amount of components by utilizing an operation processing section to compare a write address and a next instruction fetch address, thereby eliminating the need for a check section exclusive for the comparison. CONSTITUTION:A detecting section 23 detects the relation of 0<FAR-SAR<N when data contents FAR and SAR of a fetch address data and a storage address register 6 are within N (instruction buffer number X 1 instruction length). Moreover, a sequence control logic section 24 controls each part of a processing unit. A write address is fed from an operating processing section 21 to a storage section 1 by an instruction. This is operated by an operating device 11 and then the result is set to a write data register 5 and a register 6 via a register 15. The content of working register and the said register 9 is fed to routes A, B of the operating device 11 at an idle time between address and data transfer to attain the said detection. Thus, the operating processing section 21 informs it to an instruction control section 20 so as to raise a refetch request.
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