| 摘要 |
PURPOSE:To accurately perform the formation of an E-mode FET element and D-mode FET element and the formation of gate electrodes in the same steps by providing the gate electrodes of the E-mode FET element in contact with an electron supply layer. CONSTITUTION:A polygonal line E is E-mode, a polygonal line D is D-mode in the state of the gate electrode forming region. There is large etching speed difference between GaAs and AlGaAs, and since the thicknesses of both AlGaAs layers 16 and 15 are equal, the time when the E-mode side etching arrives at AlGaAs electron supply layer 12 and the time when the D-mode side etching arrives at AlGaAs semiconductor layer 14 substantially coincide, and gradually advance at the equal speed in both regions of the later etching. The total thickness of the layers 13, 14 is grown equally to the difference of the distance intended between the both mode gate electrodes and channel layers, thereby simultaneously completing the recess formation of the E-mode and D-mode spontaneously. |
