| 摘要 |
PURPOSE:To enable the accurate and easy defective analysis of largescaled master slice logic by a method wherein a monitor element with the matrix-form arrangement of required logic operational elements is prepared in the same process with a desired semiconductor element, and then analyzed. CONSTITUTION:A wafer lot is composed of a semiconductor substrate 1 to be processed and a monitor substrate 2 and then subjected to the process of element formation; thereby, the same processing as that for the former substrate is achieved to the latter substrate. NAND gates 4 and output circuits 5 are both connected to input terminals V00-Vn in one of input terminals, and the other is connected to a NAND gate of the front step. The output of the NAND gate at the final step is connected to output terminals H01-Hm via output circuits, respectively; and, is inputted to one of the NAND gate at the first step, thus constructing a ring oscillator in every column. The analyzation of the monitor elments 3 is carried out by investigating the output signal of each output terminal H01, H02,..., and Hm while signals are given to respective external input terminals V00, V01,..., Vn. |
