| 摘要 |
PURPOSE:To quicken the decision of a branch condition by processing a branch instruction branched to a designated address by means of a pipeline to allow an address generating circuit to perform the addition of an index and an increment and the comparison of an added value and a compared number. CONSTITUTION:The address generation circuit is used for not only the addition between the index of the 1st operand and the increment for but also the comparison with a compared number, and the processing using the operating section executed at a P5 stage decides a branch earlier. A value of a conventional register represented at a B2 is set to a BR (base register) 1 at a P2 stage of the 1st flow by a branch instruction and a value of D2 is set to a register 3. A 3- input adder 4 generates a branch destination address and sets it to an instruction address register 11 at a P3 stage, gives a read request of the branch destination instruction at address generation of a P2 stage and starts an instruction extracting pipeline.
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