| 摘要 |
PURPOSE:To shorten signal retardation time, and to obtain a three transistor type dynamic RAM, the speed of operation thereof is fast, by sharing the specific sections of connecting sections among two word lines of wirting and reading, two bit lines of writing and reading and an MOSFET for writing, reading and memory in an RAM cell consisting of these lines and MOSFET. CONSTITUTION:A junction section 3-1 between a reading bit line 6-1 (RB) and a diffusion layer 2 and a junction section 3-2 between a writing bit line 6-2 (WB) and the diffusion layer 2 are each arranged to two sides opposed when one cell takes a quadrilateral. Consequently, two FET elements which have not operated logically are removed, and capacitance attached to each word line 1-1 and 1-2 is reduced to approximately half. Wiring width except gate section in FET elements in several word line is widened partially as a call area is left as it is, its resistance is lowered, and the speed of operation is increased. The capacitance of each word line is also reduced to approximately half or two third at the same time, and the signal retardation time of the word lines is shortened. |
