发明名称 |
PHASE LOCKED LOOP CIRCUIT |
摘要 |
PURPOSE:To eliminate the discontinuity of a clock signal by selecting one of plural input signals and at the same time switching and controlling the division ratio for a phase comparing means which produces the control voltage according to the phase difference between an output obtained by dividing the output of a voltage control oscillator and the input signal. CONSTITUTION:Input signals IN-1 and IN-2 which are asynchronous with each other are selected alternatively by an input selection switch 3 and supplied to a phase comparator 4. The output of the comparator 4 is turned into the control voltage of a voltage control oscillator 6 via an LPF5. The output of the oscillator 6 is turned into a clock signal and also supplied to a divider 7. The divider 7 has division ratios 1/N and 1/M. These ratios are selected by a switch 8, and the comparator 4 detects the phase difference from the input signal. With interlocking control of both switches 3 and 8, the output of the oscillator 6 changes gradually according to the transient response characteristics of a PLL circuit. |
申请公布号 |
JPS6076812(A) |
申请公布日期 |
1985.05.01 |
申请号 |
JP19830185430 |
申请日期 |
1983.10.04 |
申请人 |
NIPPON DENKI KK;NIPPON DENSHIN DENWA KOSHA |
发明人 |
SANO YASUSHI;KURODA HIDEO;TAKEGAWA NAOKI |
分类号 |
H03L7/10;H03L7/08;H03L7/199 |
主分类号 |
H03L7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|