| 摘要 |
<p>A multi-processor system formed of a plurality of intelligent processing nodes interconnected by one or more transmission lines to form a shared resource cluster provides two levels of modularity which facilitate system design and growth requirements. Within each node a synchronous exchange bus interconnects processors, I/O controllers, memory controllers and serial multiplexer controllers in any combination up to a maximum total number of units, all microprocessor controlled except for global memory and the like. Each microprocessor controlled unit connected to the synchronous exchange bus includes random access memory which is functionally divided into a first portion for storing instructions and data for the on-board processor and a second portion acting as a global memory accessible by other processor controlled units on the bus. Memory address assignment for the global memory portion of each unit memory is stored in the unit in a register which is accessible by other units, so that the system can reconfigure memory address assignments by re-writing the memory address assignment in the on-board register via the bus or directly from the on-board processor. An I/O or slot address is assigned to each board as it is plugged into the bus via bus identification lines and this I/O or slot address is used to access the board for memory address assignment.</p> |
