| 摘要 |
PURPOSE:To eliminate the need for a special synchronizing circuit by forming a synchronizing signal as a signal synchronized surely with the bit period of a reception data at the reception of a mark data to synchronize surely the reception side with the transmission side. CONSTITUTION:A clock I1 having a frequency twice the data speed is frequency- divided into a 1/2 frequency by a frequency divider circuit 1 and the result is outputted as a transmission clock O2. When an inverting signal of a transmission data I2 and the reception clock O2 are inputted to an OR circuit OR and an ORed signal (a) is inputted to a flip-flop 2, a frequency modulation signal O1 is outputted in synchronizing with the clock I1. A polarity change detecting circuit 3 outputs a signal (b) representing the changing point in polarity of a modulation signal I3. A synchronizing signal generating circuit 6 outputs a synchronizing signal (d) by using the said signal (b), and an output (c) from a counter 4. The synchronizing signal (d) specifies the start timing of count to the coutner 4, and specifies the transmission timing of the reception data to a reception data regenerating circuit 5. |
