发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To eliminate the need to switch modes of memories, and to improve operativity by using two memories which are supplied with the same addresses partially or entirely to attain data accessing to one memory with a program in the other memory. CONSTITUTION:When a control part 3 sets an ROM mode line 15 and a code flag line 16 to 1, an AND circuit 4 holds a chip enable signal 18 at 1 and an ROM1 is enabled. An instruction word identification table is referred to for an instruction read out by the control part 3, and it is decided whether data access to the instruction word is attained or not; when so, the ROM mode line 15 and a data flag line 17 are both set to 1, an AND circuit 5 outputs 1, which is inputted to an OR circuit 6 together with the output 0 of an inverter 7 to hold a chip enable line 19 at 1, enabling an ROM2. When no data access is attained, the mode line 15 and the flag line 16 are set to ''1'' to enable the ROM1. Consequently, the ROM1 and RAM2 are selected automatically and a test is taken with the memory of the ROM1 regardless of overlap of addresses.
申请公布号 JPS6029854(A) 申请公布日期 1985.02.15
申请号 JP19830137504 申请日期 1983.07.29
申请人 HITACHI SEISAKUSHO KK 发明人 IKUMA JIYUNICHI
分类号 G06F11/22;G06F12/06 主分类号 G06F11/22
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