| 摘要 |
A number of techniques are disclosed to enable the manufacture of ultra high capacity three dimensionally arranged integrated circuits. For one embodiment these techniques may include: 1) Layer to layer power clocking. 2) Multilayering by the total vertical parallel connection of identical sections. 3) Reliable lamination of integrated circuit sections by including a "hydraulic" cushion between each section 4) with thermally resilient vertical interconection via the intermediary of a stackable semiconductor bonding tape. 5) Handling individually fragile sections by gravity control. 6) Yield enhancement by multilayering ready fabricated sections which have already passed functional test. 7) Mass vertical interconnection of semiconductor carriers by capillary action soldering from the outer segmented faces of the stack of sections and, 8) for some versions, cooling the product during use by enclosing a long string of stacked sections in a tube through which coolant fluid is pumped cyclically. |
