发明名称 |
A phase lock loop with idle mode of operation during vertical blanking |
摘要 |
In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period. |
申请公布号 |
AU7393494(A) |
申请公布日期 |
1994.11.21 |
申请号 |
AU19940073934 |
申请日期 |
1994.04.19 |
申请人 |
RCA THOMSON LICENSING CORPORATION |
发明人 |
DONALD JON SAUER;WILLIAM RODDA;EDWARD RICHARD CAMPBELL III |
分类号 |
H03L7/08;H03B1/00;H03B5/20;H03B5/24;H03K3/354;H03L7/093;H03L7/099;H03L7/10;H03L7/113;H03L7/14;H04N5/12;H04N5/445;H04N5/45;H04N7/12 |
主分类号 |
H03L7/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|