发明名称 INTERNAL TIMER PROCESSING METHOD OF COMPUTER SYSTEM
摘要 PURPOSE:To average a load and to reduce delay in operation by shortening the detection processing period of the internal timer processing method of a computer system to <=1sec, reducing the number of devices to be checked, and omitting error detection processing at a changing point of seconds. CONSTITUTION:When a processing routine is entered, how many times processing is performed from a changing point of seconds is discriminated on the basis of its frequency data (i); when (i) is 10, then error detection processing is omitted, and when (i) is not 10, then a device number devn is set to (i). When (i) is larger than the number of devices, the error detection is omitted, and when smaller, the decision on whether an error is present to a corresponding device or not is made; when the error is detected, the error processing is performed, and when not, a numeral 9 is added to the devn to obtain a new devn. The error detection processing is started ten times in every second and not carried out at changing points of seconds. The load on the device error detection processing upon a CPU is averaged and other operation delay is reduced.
申请公布号 JPS605357(A) 申请公布日期 1985.01.11
申请号 JP19830113292 申请日期 1983.06.22
申请人 MEIDENSHA KK 发明人 MORIMATSU KOUICHI;WATANABE SHIGEO
分类号 G06F11/30;G06F11/34;(IPC1-7):G06F11/30 主分类号 G06F11/30
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