| 发明名称 |
PIPELINED MICROPROCESSOR WITH DOUBLE BUS ARCHITECTURE |
| 摘要 |
<p>A two-bus, two instruction type, pipelined microprocessor having a control means which orders application of instruction and data addresses to a memory and further interleaves instructions and data on a single bus to achieve maximum efficiency in operation.</p> |
| 申请公布号 |
CA1180455(A) |
申请公布日期 |
1985.01.01 |
| 申请号 |
CA19820410913 |
申请日期 |
1982.09.07 |
| 申请人 |
RACAL DATA COMMUNICATIONS INC. |
发明人 |
KROMER, PHILIP F., III |
| 分类号 |
G06F9/30;G06F9/355;G06F9/38;G06F13/00;(IPC1-7):G06F9/38;G11C7/00 |
主分类号 |
G06F9/30 |
| 代理机构 |
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