| 摘要 |
PURPOSE:To improve the transmission efficiency by attaining the transmission when other device does not transmit data for a prescribed time in addition to the normal transmission start condition in a data communication processor utilized for sequential control or the like. CONSTITUTION:A reception signal RXD inputted from a transmission line 20 is supplied to a synchronism circuit 102, where the signal is synchronized with a clock from a clock generator 107, the clock synchronized with the reception signal RXD is given to a control circuit 101 and the reception signal is read in a shift register 104 by a signal of the control circuit 101. The address of a prescribed bit of the shift register 104 is compared by an address comparator circuit 103, and in case of coincidence, the reception signal is transferred to an I/O buffer. Further, a signal from the I/O buffer is transmitted via a register 104 as a transmission signal TXD after the transfer. Moreover, even if the reception signal does not exist for a prescribed time, the signal from the I/O buffer is transmitted. |
