| 摘要 |
<p>PURPOSE:To reduce remarkably the number of elements constituting a decoding circuit and improve the operation speed of the circuit, by providing decoding circuits of a number corresponding to the number of single bit information expressed by encoded data and dividing plural bit information constituting encoded data into higher bit information and lower bit information. CONSTITUTION:Decoding circuits U1 and U2 are composed of P-channel MOS field effect transistors (TRs Q1 and Q2 which are connected with each other in parallel and N-channel MOS field effect TRs Q3 and Q4 which are connected with each other in series, respectively. Therefore, the decoding circuits U1 and U2 can be constituted with four MOS field effect TRs Q1-Q4 which are double of the bit number of the lower 2-bit information. Decoded inputs A0 and A1 of lower 2-bit are distributed to the gates of MOS field effect TRs Q1 and Q2 which are connected with each other in parallel or Q3 and Q4 which are connected with each other in series. Depending on the combination of the distribution, a single bit decoded output D0 is actuated only when a specific bit pattern is set.</p> |
