发明名称 FOUR-LEVEL INPUT DECISION CIRCUIT
摘要 PURPOSE:To obtain a four-level input decision circuit which decreases current sources, reduce power consumption, and outputs an optimum signal by using three differential amplifiers which are connected properly. CONSTITUTION:When an input voltage VIN is between 0 and V1 (threshold voltage), transistors (TR) 1 and 5 turn on and a TR6 turns off, so TRs 3 and 4 also turn off to hold output terminals 16 and 17 both at L. When the input voltage VIN is between V1 and V2 (threshold voltage), between V2 and V3 (threshold voltage), or between V3 and VCC, the output terminals 16 and 17 are at L and H, H and L, or H and H. Therefore, this four-level input decision circuit requires no constant current source and only two branches are necessary for current sources, so the power consumption is reduced and the state of an output signal is inverted between a maximum and a minimum value, so that the optimum output signal is obtained.
申请公布号 JPS59212031(A) 申请公布日期 1984.11.30
申请号 JP19830087301 申请日期 1983.05.18
申请人 NIPPON DENKI KK 发明人 MASHITA MAKOTO;AMANO TATSUYUKI
分类号 H03M5/20;G11B20/10;H03K19/082;H03K19/0944;H03K19/20 主分类号 H03M5/20
代理机构 代理人
主权项
地址