| 摘要 |
PURPOSE:To increase the addition speed by using two 5-input logical gates, a 2-input logical gate and a 3-input logical gate to constitute a full adder. CONSTITUTION:Two 5-input (a-e) CMOS logical gates 1 and 2 have an output f=0 when a=b=c=1 or a=d=e=1 is satisfied and an output f=1 when a=b= c=0 or a=d=e=0 is satisfied. A 2-input (g, h) logical gate 3 has an output K=0 with g=h=1 and an output K=1 with g=h=0. A 3-input (l, m, n) logical gate 4 has outputs k=0 and k=1 with l=m=1 and l=n=0 respectively. An addition signal A, a signal B to be added and a carry input signal Ci are used as inputs to obtain an addition output S and an output signal Co. In such constitution, the addition is possible at a speed about double as high as the conventional value. |
