发明名称 OPERATIONAL AMPLIFYING CIRCUIT
摘要 PURPOSE:To prevent the fluctuation of the gain and frequency band due to the offset control by cascading an adverse conduction type transistor TR to the collector of a differential amplifying TR, providing a load circuit including an offset control circuit at the emitter side of the amplifying TR and making use of the impedance converting function of the cascaded TR. CONSTITUTION:The collectors of differential amplifying transistors TRQ3 and Q4 are connected to the collectors of TRQ1 and Q2 respectively. The bases of the TRQ3 and Q4 are used in common with each other, and at the same time the base and the collector of the TRQ3 are used in common with each other. Then the TRQ3 and Q4 have current mirror forms. A loading means including an offset control circuit is provided to the emitters of the TRQ3 and Q4 respectively. This offset circuit is provided with, e.g., control resistances Ra, 2Ra and 4Ra, Zener diodes D1, D2 and D3, a control resistance 8Ra and a Zener diode D4. These diodes D1-D4 short-circuit selectively the resistances Ra-8Ra in response to the offset. In such a way, the synthetic resistance value is controlled to ensure offset.
申请公布号 JPS59208915(A) 申请公布日期 1984.11.27
申请号 JP19830082617 申请日期 1983.05.13
申请人 HITACHI SEISAKUSHO KK 发明人 NAGAYAMA YOSHIHARU
分类号 H03F3/34 主分类号 H03F3/34
代理机构 代理人
主权项
地址