发明名称
摘要 <p>PURPOSE:To simplify the clock control of a digital computer by controlling the start and stop of the generation of control clocks and the continuation of several periods by using the each-digit output of control and free clock counters to advance control clocks and free clocks. CONSTITUTION:Through the control with a fundamental clock period taken as 1T, the (n)-number control clocks of periods 1T, 2T... 2n+T are generated and supplied as free clock of periods 1T, 2T...2n-1T which do not control the generation. At this time, each-digit outputs of n-bit binary counter controlled respectively and n-bit binary counter whose advance is not controlled are used to advance those control clocks and free clocks. When the controller restarts the generation of control clocks after a temporarily break, the content of the control counter is compared with that of the free counter and after the advance of the control counter is restarted, the advance start timing of the control counter is determined so as to equalize the both counter in content.</p>
申请公布号 JPS5947334(B2) 申请公布日期 1984.11.19
申请号 JP19780097661 申请日期 1978.08.10
申请人 FUJITSU LTD 发明人 IWATO MASATAKE
分类号 G06F1/06;G06F1/04 主分类号 G06F1/06
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