发明名称 DIAGNOSING SYSTEM FOR TERNARY LOGIC ELEMENT
摘要 PURPOSE:To achieve an accurate judgement on the circuit condition involving the high impedance state by diagnosing the output time twice, for a long and short periods, to make the high impedance recognisable at the output pin of a ternary logic element. CONSTITUTION:As a logic ternary at a high level, a low level and a high impedance varies from the low level to high impedance through input pre-stage circuit 1 and 3 of a tristate element and a tristate element 6, the resultant voltage displacement is delayed greatly by a light discharge according to a final terminal resistance 7 and a floating capacitance of a tester and detected with an input amplifier 8. The detection output is compared with an output expected value to judge after the change in the output as specified by an expected value alternation control circuit 9 with respect to a decision circuit 10 long in the set time. On the other hand, when the set time is short, the expected value is controlled by the circuit 9 so that the output expected value of the preceding test is judged with respect to the circuit 10. With such an arrangement, the high impedance state of the ternary logic output can be recognized thereby judging the circuit condition at this state accurately.
申请公布号 JPS59198370(A) 申请公布日期 1984.11.10
申请号 JP19830072853 申请日期 1983.04.27
申请人 HITACHI SEISAKUSHO KK 发明人 ISHIYAMA TAKASHI
分类号 G01R31/28;G01R31/317;(IPC1-7):G01R31/28 主分类号 G01R31/28
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