发明名称 DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To prevent overflow by providing a means for changing the order of additions of plural digital signals in addition. CONSTITUTION:Plural delay means are formed by delaying an input digital signal and/or an output digital signal by plural stages of delay means 1 at each word for instance. A prescribed coefficient is multiplied to each delay signal by a coefficient multiplication means 2 and the result is added by an addition means 3. A means 4 for changing the order of addition is provided in order to eliminate the overflow of the means 3 or decrease the frequency. The means 4 has a function which changes the order of additions through the detection of overflow occurred in, e.g., the means 3 or decides the order of additions in advance so as not to produce overflow based on the result of multiplication of coefficients independently of the detection of overflow.
申请公布号 JPS59198020(A) 申请公布日期 1984.11.09
申请号 JP19830072501 申请日期 1983.04.25
申请人 SONY KK 发明人 TERAUCHI TOSHIROU;TAMURA SHINICHI
分类号 H03H17/02;G06F17/10;H03H17/04 主分类号 H03H17/02
代理机构 代理人
主权项
地址