发明名称 LATCH CONTROLLING SYSTEM OF DIGITAL OUTPUT
摘要 PURPOSE:To execute automatic reset by resetting a latched data, when the following data is not inputted before a timer whose period is larger than a necessary period provided on a circuit for inputting a digital output from a processor in said necessary period is operated. CONSTITUTION:A digital data is outputted from a processor 1 in a period T11 of a built-in timer TM1. A digital outputting circuit 2 inputs said digital data to a set terminal S of an FF, and sends it out as a digital signal output to a part to be controlled of the outside of the figure. A timer TM2 contained in the digital outputting circuit 2 starts to count at the same time as the timer TM1, and its count-up period T22 is set larger than T11, and it is connected to a reset terminal of the FF. In this way, when the following digital data is not inputted before attaining to a time-out period T22 due to a fault of software, etc.; the FF is reset, the digital signal output is stopped, the automatic reset is executed, and the device is protected.
申请公布号 JPS59189428(A) 申请公布日期 1984.10.27
申请号 JP19830063971 申请日期 1983.04.12
申请人 FUJITSU KK 发明人 NAKAJIMA MASAAKI
分类号 G06F11/30;G06F3/00;G06F11/00;G06F13/00 主分类号 G06F11/30
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