| 摘要 |
PURPOSE:To decrease the amount of hardware by using in common the hardware of an access pipeline control section ACP-C for a load/storage instruction and a vector compression/expansion instruction. CONSTITUTION:In case of a load instruction, a data incoming from a memory MSU is arranged by a data arranging circuit and then given to a vector register VR. Further, in case of a storage instruction, the data read from the VR is arranged via a data buffer and a data arranging circuit in an alignment processing section ALC, it is transferred to the memory MSU. In executing these instructions, a transfer request signal and an address are transmitted from a memory access control section MCU in the ACP-C, the number of elements obtained via an effective element number recognizing circuit is counterd by an ELC so as to give an arranging gate signal to a data arranging circuit via an arranging gate generating circuit based on the result. On the other hand, the ACP-C in executing the vector compression/expanding instruction counts the elements via a data register MDR and a number of [1] calculating circuit. |
