| 摘要 |
A memory circuit comprises a plurality of memory cells and a plurality of sense circuits each including first and second input MOS transistors and first and second load MOS transistors of a first channel type and a load circuit connected to the sense circuit and including first to fourth load MOS transistors of a second channel type. The first and second input MOS transistors have their sources connected to each other and their gates connected to receive a differential input signal therebetween from said memory circuits of the first and second switching transistors which have their sources connected respectively to the drains of said first and second input transistors and their gates connected to a column selection signal. The first and second load MOS transistors have their drains connected in common to the drain of the first switching MOS transistors and their sources connected to each other. The third and fourth load MOS transistors have their drains connected in common to the drain of the second switching MOS transistors and their sources connected to each other. The gates of the first and fourth load MOS transistors are coupled respectively to the drains of the first and second switching MOS transistors, and the gates of the second and third load MOS transistors are cross-coupled to the drains of the second and first switching MOS transistors, respectively.
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