Multi-port memory cell and system.

摘要

A memory cell for storage arrays, e.g. register stacks, which comprises a plurality of write (28, 29) and read (30, 31, 32) transistors coupled to a single storage cell (35) or its output amplifier (33), respectively. Each of the write and read transistors is separately selectable by an address decode signal on a respective control line (17A, 18A, 19A, 20A, 21A). Each of the write transistors (28, 29) is connected to an associated write head (12, 13), and each of the read transistors (30, 31, 32) is connected to a respective read head (14, 15, 16). Thus, the cell can be written and read within one cycle, and also multiple simultaneous read-outs are possible.