| 摘要 |
<p>PURPOSE:To suppress jitter due to a signal pattern, and also to generate no phase shift by using the rise point in a specified pattern of a transmission code in order to adjust the phase of a timing synchronizing signal for discriminating the transmission code. CONSTITUTION:A received bipolar code transmission signal is inputted to a discriminating circuit 11 as a roll-off-formed equalizing output S1, also inputted to a full-wave rectifying circuit 12, and rectified. An output S1' of the circuit 12 is brought to waveform shaping in a limiting circuit 13 by setting a point of 50% of a peak value as reference voltage VREF. This output S2' is inputted to a DPLL circuit 15 through an AND circuit 14, and its output clock S3 is controlled by basing on a rise point of an output S2 of the AND circuit 14 as a reference. An output S4 of a code discrininating circuit 11 is inputted to a delaying circuit 17 through an inverting circuit 18. In this case, basing on a master clock from a master clock generating circuit 16, an inverted output code is delayed by a prescribed delay quantity, and its output S5 is inputted to the AND circuit 14.</p> |
