| 摘要 |
<p>PURPOSE:To transfer data at a high speed among plural digital signal processors via a common bus by securing synchronization among all digital signal processors. CONSTITUTION:The common clock CLK and synchronizing pulse SYNC are supplied to digital signal processors DSP1-DSP3 for synchronizing operations. Under such conditions, the data is transferred to the DSP2 from the DSP1. In this case, an instruction OUT which is delivered to a common bus L1 is written to the DSP1. While a transfer instruction which is given to an internal register from the bus L1 is written to both DSP1 and DSP2. In such a way, the data can be transferred via a common bus.</p> |
