发明名称 PIPELINE TYPE PROCESSOR
摘要 A pair of inherently sequential instructions, having an instruction dependency of the type in which the subsequent instruction requires as an input operand the result of the earlier instruction execution, can nevertheless be simultaneously executed by two data flow facilities (primary and secondary) under control of a control unit, without the requirement that both data flow facilities be fully equipped for all instructions. …<??>The secondary data flow facility of this invention is generally less massive and less sophisticated than the primary data flow facility but is more sophisticated in a critical organ, the adder. The adder in the secondary data flow facility has one additional operand capability. The three-input adder of the secondary data flow facility thus is capable of replicating internally a result of the two-input adder of the primary data flow facility. Using this replicated primary adder "result", together with the additional operand capability, the secondary data flow facility three- input adder executes the dependent subsequent instruction of the pair simultaneously with the earlier instruction execution by the primary data flow facility.
申请公布号 JPS59173850(A) 申请公布日期 1984.10.02
申请号 JP19840024549 申请日期 1984.02.14
申请人 INTERN BUSINESS MACHINES CORP 发明人 SHII TANGU HAO;HIYUUI RINGU;HAWAADO EDOWAADO SATSUCHIYAA;JIEFURII UEISU;YANISU JIYON YAMUA
分类号 G06F7/00;G06F9/38 主分类号 G06F7/00
代理机构 代理人
主权项
地址