发明名称 ABNORMALITY DETECTOR FOR SYMMETRICALLY ARRANGED SENSOR
摘要 PURPOSE:To detect abnormality definitely by checking whether the time from the rising of OR between signals from two symmetrically arranged sensors to the rising of AND and the time from the falling of AND to the falling of OR are within a specific range or not. CONSTITUTION:Output terminals of the sensors 3 and 3' which turn on and off almost at the same time are connected to the 1st logical circuit 10, the 2nd logical circuit 12, an inverting circuit 14, and the 4th logical circuit 16. The 1st logical circuit 10 is connected to the 3rd logical circuit 20 through the 1st pulse generator 18, the 2nd logical circuit 12 is connected to the 4th logical circuit 16 through the 2nd pulse generator 22, and the inverting circuit 14 is connected to the 3rd logical circuit 20. Signals S1 and S2 from the sensors 3 and 3' are ORed S120 by the 1st logical circuit 10 and ANDed S12A by the 2nd logical circuit 12. When the time t1 from the rising of the S120 to the rising of the S12A or the time t2 from the falling of the S12A to the falling of the S120 exceeds the specific range, the abnormality of on operation or off operation of either sensor is detected.
申请公布号 JPS59170714(A) 申请公布日期 1984.09.27
申请号 JP19830045012 申请日期 1983.03.17
申请人 KAWASAKI SEITETSU KK 发明人 ICHII YASUO
分类号 G01B21/00;G05B19/4063 主分类号 G01B21/00
代理机构 代理人
主权项
地址