Dynamic shift register utilizing CMOS dual gate transistors

摘要

A shift register using dual gate transistors is described. Each stage consists of a P-channel and and N-channel dual gate transistor interconnected to provide both an inverting function and a switching function. The gates of each stage of one set of alternate stages are clocked in one phase with a clocking voltage alternating between a low level and a high level and its inverse. The gates of each stage of the other set of alternative stages are clocked in the opposite phase with the clocking voltage and its inverse.