发明名称 SIGNAL PROCESSOR
摘要 PURPOSE:To miniaturize a signal processor by multiplying the frequency of an input signal through the 1st multiplying circuit, selecting in time division the multiplied frequency by a selecting circuit of a multiplex constitution, and outputting these selected frequencies in parallel for each type of signals. CONSTITUTION:A receiving part 10 of an automatic train control device ATC outputs ATC signals A of frequencies fa1-fan corresponding to indicated speeds a1-an. These signals A are divided into two routes. One of these two groups of signals A is supplied to a selecting circuit 30 via the 1st multiplying circuit 20, and the other group is supplied to a collating circuit 50 respectively. The circuit 30 has a multiplex constitution in terms the time division or parallel processing and processes the frequencies of input signals to deliver them in parallel for each type of signals. The circuit 50 contains a multiplying circuit 51 which is switched under the output conditions of the circuit 30 and outputs the central frequency corresponding to said output conditions to a BPF52 of the next state. The output of the BPF52 is effective when the circuit 30 has a correct output and turns on a fail-safe gate circuit 60 to permit the output of the circuit 30.
申请公布号 JPS59165551(A) 申请公布日期 1984.09.18
申请号 JP19830039404 申请日期 1983.03.10
申请人 NIPPON SHINGO KK 发明人 HOSHINO TAKEHIKO;SAEGUSA HIDETAKA
分类号 H04J1/00;B60L3/08;G05B9/02;H04L27/148;H04L27/26 主分类号 H04J1/00
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