| 摘要 |
PURPOSE:To simplify the constitution of a titled system by detecting each component of a data signal and a burst synchronizing signal from a receiving signal and its delay signal to transmit in time series each signal of data, clock and burst synchronism on a single transmission line. CONSTITUTION:A data signal (a) of unipolar NRZ, a burst synchronizing signal (b) and a clock signal (d) are synthesized at a synthesis circuit 14 and become a base band signal (f) and transmitted to the receiving side via a transmission line 22. The signal (f) is fed respectively to a half bit delay circuit 24 and a 1- bit delay circuit at the receiving side to form a signal (g) delayed by a half bit and a signal (h) delayed by 1-bit. The signals (f), (g), (h) are applied to a clock extracting circuit 28, a data reproducing circuit 30 and a data burst timing detecting circuit 32. Then, a clock signal (j), a data signal (k) and a data burst timing signal (l) are detected respectively separately. |
