FABRICATION OF MOS INTEGRATED CIRCUIT DEVICES

摘要

In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects are designed to make contact with ohmic regions in the single-crystalline body (10) of the device. In accordance with a simplified fabrication procedure, a single implantation step is utilized to dope the metallic silicide (34, 36) while doping selected portions of the body. During a subsequent heating step, source (48), drain (48) and ohmic contact regions (50) are formed in the body. During the same step, the dopant in the metallic silicide diffused into underlying layers of polysilicon (42) and into body portions (52) directly underlying polysilicon in amounts sufficient to render the polysilicon conductive and to form additional ohmic contact regions in the body.