发明名称 ARRAY MULTIPLIER
摘要 PURPOSE:To perform a quick divisional operation by detecting the decoded signal of a multiplier at the divisional operation time and generating an increment signal when a multiplicand is negative and selecting the increment signal for divisional operation and selecting the multiplicand for non-divisional operation. CONSTITUTION:A multiplying array is divided into several array blocks 121.... Operating cells C11-Cij are arranged in each of blocks 121.... Each of cells C11-Cij consists of a selector SEL1 to which Xi, the inverse of Xi, etc. are inputted, a selector SEL2 to which the output X' of the selector SEL1, an increment signal INC, etc. are inputted, and a full adder FA to which the output X'' of the selector SEL2, a sum signal S, and carry C are inputted. The decoded signal of the multiplier is detected for divisional operation and the signal INC is generated when the multiplicand is negative. The selector SEL2 selects the signal INC for divisional operation and selects the signal X' for non-divisional operation. Thus, the quick divisional operation is performed.
申请公布号 JPS6267637(A) 申请公布日期 1987.03.27
申请号 JP19850207817 申请日期 1985.09.20
申请人 TOSHIBA CORP 发明人 IKUMI NORIYUKI
分类号 G06F7/533;G06F7/506;G06F7/52;G06F7/53 主分类号 G06F7/533
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