发明名称 FAULT DETECTING SYSTEM
摘要 PURPOSE:To detect easily the fault of an operator by providing a tester to plural operators to execute a part of operations which are carried out by those operators, then collating the results of operations with each other. CONSTITUTION:An input data 10-12 of an adder/subtractor circuit 1 and an input data 20-22 of a multiplier/divider circuit 2 are selected in response to the output of a random number generating circuit 4 and then set to an input sample register 30-32. The output of the register 30-32 is supplied to a tester 3; while the output of the circuit 4 is sampled by an operator identifying register 40. The output of the register 40 is used as the input of an output sample register 50, i.e., an input switch signal of outputs 13 and 23 of circuits 1 and 2 respectively. A test circuit 5 gives addition, subtraction, multiplication or division to the values of registers 30 and 31 in accordance with indications of registers 32 and 40 and then delivers the sum, difference, product or quotient to the output data 33. The output of the register 50 and the output 33 of the tester are supplied to a comparator 5 for mutual collation.
申请公布号 JPS59135552(A) 申请公布日期 1984.08.03
申请号 JP19830009581 申请日期 1983.01.24
申请人 NIPPON DENKI KK 发明人 MATSUMOTO HAJIME
分类号 G06F11/18;G06F11/14;G06F11/16 主分类号 G06F11/18
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