| 摘要 |
PURPOSE:To decrease the area of the entire circuit and chip size by forming an inverter forming a false level signal in an address decoder circuit to reduce the occupied area of the address buffer circuit and the area of wiring area to the address decoder circuit. CONSTITUTION:When internal address signals ay1-ayn of reverse level are applied to wirings 4y1-4yn of a true system from an external address buffer circuit 3, the signals ay1-ayn are inverted by inverters 5y1-5yn to form signals ay1'-ayn' of false level. The signals ay1'-ayn' of the false level are applied respectively to wirings 4y1'-4yn' of the bar system respectively. Thus, the inverters 5y1-5yn are formed in the region surrounded by chain lines not formed for any circuit element conventionally. Thus, even if the inverters 5y1-5yn forming the address signals ay1'-ayn' of the false level are provided in an address decoder circuit, the area of the address decoder circuit is not increased. |
