| 摘要 |
PURPOSE:To remove the limit of the operation speed of an RAM, to reduce the power consumption, and to use an inexpensive RAM by converting input data from serial to parallel temporarily, and converting the operation speed into a speed lower than the maximum operation speed of a memory and then accessing the RAM. CONSTITUTION:Data inputted from a data input terminal A is inputted to a serial-parallel converter 3 according to a clock inputted successively from a clock input terminal B. The clock from the clock input terminal B is frequency- divided by four through a 1/n frequency divider 5 to perform clock conversion. The output of this 1/n frequency divider 5 is inputted to the RAM6 as its read/ write control signal and also is inputted to an address counter 7 as its counting clock. The RAM6 reads data out of an address of the RAM6 specified by the address counter 7 at the rising of the output of the 1/n frequency divider 5 and the stored data is outputted to a parallel/serial converter 4 in parallel. |
