| 摘要 |
PURPOSE:To decrease the bit shift occuring in the change in a duty or the fluctuation in a base line by detecting the time difference between a reading out signal and a clock signal according to the polarity of a reproduced analog signal, and controlling the threshold value of a comparator to minimize the time difference between both polarities. CONSTITUTION:A reading out signal (b) and a clock signal (c) are inverted by inverters 6, 7, and the reading out signal and clock signal of both polarities are supplied to D type FFs 8-15. Then the time pulse proportional to the time difference TER between the signal (b) and the center of the signal (c) at the rising polarity of the signal (a) is obtd. from the output (d) and the output (e), and a time difference signal (h) at the rising polarity is formed in an OR circuit 16. A time difference signal (i) is similarly formed. The differential signal (j) of both signals is then obtd. and is inputted as a threshold value voltage via an LPF19 to a compartor 3. If the threshold value voltage is higher than an optimum value, the pulse width on the negative side of the signal (j) is longer than the positive side TER and the negative voltage of the time difference is supplied to the comparator 3. The threshold voltage obtains a correct duty. The reading out following up the fluctuation in the base line of the signal (a) is performed by setting the breaking frequency of the LPF19 and an amplifier circuit 2. |
