发明名称 MASTER SLICE TYPE INTEGRATED CIRCUIT GROUP
摘要 PURPOSE:To contrive accomplishment of the layout design of the titled integrated circuit group in a highly efficient manner by a method wherein the channel width of the wiring located between functional blocks of the first kind and second kind master slice type ICs is variedly formed each other. CONSTITUTION:In two kinds of master slice type chips (a) and (b), the quantity of cell 1' in X and Y directions, which can be contained in one circuit functional block, is limited to P-pieces and q-pieces, and the blocks 3' and 4' are limited in size. The intercell distances l' and m' are made equal between the two chips (a) and (b) at the limit value or below, the group 5 consisting of the number of cells within the limit value is considered as 1 unit, and the intergroup distances (h), (i), (j) and (k) are independently established in the amount required for the chips (a) and (b). According to this constitution, circuit functional blocks can be used common between a plurality of master slice type ICs. Also, as cell groups are formed common in size, they can be made into macroscopic form by performing an interconnection, thereby enabling to obtain a layout structure suitable for multilayer automatic design.
申请公布号 JPS59107537(A) 申请公布日期 1984.06.21
申请号 JP19820217956 申请日期 1982.12.13
申请人 NIPPON DENKI KK 发明人 ITOU SOUICHI
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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